1. Field of the Invention
The present invention relates to a programmable logic device, and in particular to a sense circuit having a wide AND gate mode or a zero power single input function mode.
2. Description of the Related Art
FIG. 1 illustrates a conventional programmable logic device (PLD) sensing circuit 100 having a plurality of memory cells 107, 108, 113, and 114 to provide a wide AND gate functionality. Typically, sensing circuit 100 uses either electrically programmable read only memories (EPROMs) or electrically erasable programmable read only memories (EEPROMs) for memory cells 107, 108, 113, and 114.
An EPROM includes a floating gate FG, a control gate CG, a source S and a drain D (see memory cell 107 for reference). Floating gate FG is isolated from control gate CG by an insulating material. To program an EPROM, i.e. to store a zero at this memory cell, a high voltage is applied to control gate CG and drain D and a low voltage is applied to source S, thereby causing electrons to flow from source S to drain D of the EPROM. If this current is sufficiently large, a small number of electrons attain sufficient energy to traverse the insulating layer between the channel and floating gate FG, thereby resulting in a negative charge accumulation on floating gate FG. After the high voltage is removed, this negative charge remains on floating gate FG which increases the threshold voltage of the EPROM. Thus, during subsequent read operations, a fully programmed EPROM will not turn on even if it is selected. An EPROM is erased by exposing the cell to ultraviolet light, thereby providing sufficient energy for the trapped charge to escape. An EEPROM, which is similar in configuration to an EPROM, is erased electrically by applying a low voltage to floating gate FG and source S and applying a high voltage to drain D.
As shown in FIG. 1, signals A and B are provided to input lines 101 and 102, respectively. Signal A is inverted by inverter 103 and then provided to the control gate of memory cell 107 via line 104. The complement of signal A, signal A is inverted by inverter 105 and then provided to the control gate of memory cell 108 via line 106. In a similar manner, signal B is inverted by inverter 109 and then provided to the control gate of memory cell 113 via line 110, and the complement of signal B, signal B, is inverted by inverter 111 and then provided to the control gate of memory cell 114 via line 112. Each of memory cells 107, 108, 113, and 114 is coupled between a low voltage source (typically ground) and a bit line 120.
Sensing circuit 100 includes a p-type transistor 116 having its drain D and its gate G connected at node 115. The source S of transistor 116 is coupled to a high voltage source Vcc. In this configuration, transistor 116 provides a pull-up of the voltage at node 115. Typically, transistor 116 is sized to provide a weak voltage pull-up. Node 115 is coupled to the drain D of n-type transistor 121, whereas the source S of transistor 121 is coupled to bit line 120. Gate G of transistor 121 receives a reference voltage Vref which is typically 2.7 volts, thereby turning on transistor 121. Transistor 121 limits the voltage swing on bit line 120 to between approximately zero volts and 1.8 volts. The voltage at node 115 is amplified by inverters 117 and 118 to provide a full CMOS level output signal Y on output line 119.
In this configuration, if any one of the memory cells 107, 108, 113, or 114 is unprogrammed and is subsequently selected (i.e. provided with a high voltage on its control gate CG), that unprogrammed cell turns on, thereby providing a strong pull-down of the voltage on bit line 120 and node 115 (via transistor 121) and overpowering the weak pull-up provided by transistor 116. In this manner, a wide-fanin AND function is provided. For example, if sense circuit 100 is used to implement the function Y=A.multidot.B, memory cells 107 and 114 are left unprogrammed while all other memory cells on bit line 120 are programmed.
Wider fanin logic functions are implemented by increasing the number of memory cells on bit line 120. Specifically, a sense circuit that provides a fanin of N input lines (wherein N is an integer) requires 2N memory cells coupled to its bit line, i.e. each memory cell having a control gate coupled to either the true or complement polarity of the signals on the N input lines.
In this configuration, a continuous DC current is drawn as long as the voltage on bit line 120 is pulled low by one or more unprogrammed, selected memory cells coupled to bit line 120. However, not all applications require a sense circuit having a wide fan-in functionality. In fact, many applications require only a simple input/output connection. In those applications, the continuous DC current in sensing circuit 100 results in a significant power draw. Therefore, a need arises for a sense circuit that selectively provides a wide fan-in functionality in one mode and a zero power single connection in another mode.